In a computer system, a cache memory capable of high-speed read/write operation is used to fill the speed gap between a central processing unit (CPU) and a main memory.
The cache memory holds a part of the data stored in the main memory. The set-associative memory is an example of the cache memory. The cache memory includes a tag RAM for holding the address (tag) indicating the storage position of the cache data on the main memory and a data RAM for holding cache data. The tag RAM and the data RAM have such a data structure that a plurality of cache lines correspond to each of the blocks into which the main memory is divided and have as many parallel ways as the cache lines. At the time of accessing the data, the same block covering the ways is generally accessed.
In designing the cache memory, the legitimacy of the logic design is verified by various methods in the logic design stage of the cache.
For example, a verification device emulating a cache memory receives a memory access request of the computer in operation is known. The verification device verifies the operation logic by emulating the memory access operation.
In another known technique, the result of execution of a plurality of instructions for each machine cycle by a verification device emulating a pipelined cache memory according a logic verification program is compared with the result of executing one instruction at a time by a verification unit emulating a cache memory for sequentially executing one instruction at a time, i.e. an expectation value thereby to verify the legitimacy of the contents held in the verification device.
Examples of the references disclosing the techniques for the cache memory include Japanese Unexamined Patent Publications Nos. 2001-306397 and 2001-256270.
The conventional method of logic verification of the cache memory poses the problem that the legitimacy of the logic design of the cache memory cannot be efficiently verified. Specifically, when the data is read from the cache memory, the process is executed in stages to judge whether the data is held in the cache memory or not, and therefore, which one of a plurality of stages of the reading process is erroneous cannot be efficiently verified. In order to positively verify which stage is erroneous, the main memory and the cache memory are required to be prepared for each stage to clarify whether the operation in each stage is correct or erroneous. This measure, however, complicates the logic verification and requires many verification steps.